A typical board design development for a communication application requires many discrete modules or chips. Among these modules are, a general purpose microprocessor, one or two DSP cores, associated peripherals such as DMA, UART, viterbi accelerator, memory including RAM or ROM and a clock generator unit capable of frequency synthesis.
Most microprocessors and DSP cores are designed based on complementary non-overlapped two phase clocks which may be run at a different operating frequency with respect to one another. Therefore, minimal clock skewing among all modules is desirable to achieve high performance. One solution that helps in minimizing clock skewing and improving performance is high integration single chip solution as shown in FIG. 1. However, many system development or application board designs rely on the use of multiple single chips prior to the high integration single chip solution which is technology driven.
Traditionally, clock generator chips used in conjunction with development of application boards can generate only a single phase clock with multiple output frequencies. Therefore, to provide a complementary non-overlapped two phase clock that is required by most microprocessors, DSP cores and peripherals, additional on board discrete components are required to generate the desired non-overlapped logic. This has a direct impact on the clock skewing which is proportional to system performance i.e., lower clock skews results in a higher performance. In addition, there may be no provision to control the clock to each processor or peripherals for power save options. In the present invention, instead of adding external discrete components to a clock generator circuit for the purpose of obtaining non-overlapped clock phases by delaying one of the clocks a sufficient amount of time to generate the non-overlap between the clock phases, a phase driver and non-overlap logic circuit is integrated on the same chip to provide a set of complementary non-overlap two phase clocks running at different frequencies. In providing support for low power, many power save features are made available within this unit.
The invention utilizes a clock signal which originates from an oscillator which is input into a set of frequency dividers or a frequency multiplier such as a synchronous delay line (SDL) to produce clock signals at frequencies required by the processors and other elements integrated on the same chip. A suitable SDL for this purpose is described in U.S. Pat. No. 4,980,585, specifically, FIGS. 2-9 of the patent which describe a suitable SDL for use with the present invention and supporting elements.